(a) Field of the Invention
The present invention relates to a semiconductor integrated circuit that employs pads providing less input signal attenuation.
(b) Description of Related Art
Junction field-effect transistors (abbreviated as J-FETS) are generally used for special applications such as condenser microphones because they have a high input impedance, compared with bipolar elements, and a high electrostatic withstand voltage, compared MOS FET elements. Moreover, J-FETs are used for small signal amplification because of less noise over low-frequencies and good high-frequency characteristics. Recently, J-FETs built in a bipolar integrated circuit are being developed.
FIG. 6 shows an integrated circuit integrating a J-FET. A signal is applied to the gate of the J-FET 2 from an external circuit via a pad 1 formed on an integrated substrate. The external input signal varies the gate voltage of the J-FET 2, thus varying the current amount flowing through the J-FET 2. The load resistance RL converts the current into a voltage to output the converted voltage.
In the integrated circuit shown in FIG. 6, two parasitic capacitance components occur between the pad 1 and the substrate. Referring to the cross section of an integrated pad shown in FIG. 7, an island region 102 is defined between two isolation regions 101. A metal 103 is formed over the island region 102. In such an integrated configuration, a MOS capacitance (or parasitic capacitance) 3 is formed between the island region 102 and the metal 103. A junction capacitance (or parasitic capacitance) 4 is formed between the island region 102 and the substrate. The juncture between the pad 1 and the gate of the J-FET 2, as shown in FIG. 3, is grounded via the parasitic capacitances 3 and 4. Where an element with a high output impedance, for example, a capacitor of a small capacitance, is connected to the pad 1, both the parasitic capacitances 3 and 4 may appear as a very large capacitance, compared with the small capacitor. Particularly, when the area of the pad 1 is made large to use the circuit of FIG. 3 for a special application, the parasitic capacitance becomes even larger so that the difference between the capacitance of the small capacitor and the parasitic capacitance becomes noticeable. As a result, since the pad 1 attenuates the input signal applied to the gate of the J-FET 2, it is difficult to erroneously obtain the input signal.
This invention is made to overcome the above-mentioned problems. It is an object of the present invention to provide a semiconductor integrated circuit including pads each with a high input impedance and with a low capacitance.
The pad is connected to a buffer circuit that charges and discharges the parasitic capacitance. Thus, the charging amount of the parasitic capacitance varies according to an input signal so that attenuation of an input signal can be prevented.
The pad is connected to a source follower circuit that charges and discharges the parasitic capacitance. Thus, the charging amount of the parasitic capacitance varies according to an input signal so that attenuation of an input signal can be prevented.